Varactors are voltage-tunable capacitors whose capacitance varies as a function of an applied voltage. Varactors often comprise multiple voltage-tunable capacitor cells, with each cell having a capacitive range, wherein the net capacitive range of the varactor is substantially equal to a sum of the capacitive ranges of the individual capacitor cells. Examples of varactors in monolithic integrated circuit implementations include a varactor diode employing a p-n junction in reverse bias, and a metal-oxide semiconductor (MOS) inversion mode varactor.
Varactors are commonly employed in voltage-controlled oscillators (VCO's) as the principal control element for tuning the output frequency of an analog or mixed-signal phase-locked loop (PLL) so as to match an input reference frequency. A PLL is a negative feedback control system for matching the phase of a generated output clock to that of an input reference clock. For PLL's with low jitter requirements, such as those utilized in high-speed serial data transmission, both coarse and fine control of the VCO are required, as a single line control is generally not sufficient. For coarse and fine control, the capacitor cells of the VCO's varactor are segregated into two groups, with one group controlled via a coarse control input and the other via a fine control input, wherein the net capacitance of the coarse control group is generally much larger relative to the net capacitance of the fine control group.
Coarse control provides the tuning range necessary for the PLL to lock to its input reference amidst process, power supply voltage, and temperature (PVT) fluctuations; uncertainties in circuit modeling during the design process, and flexibility to adjust the input reference frequency for system test purposes. Fine control, with its smaller effect on the VCO output, allows the PLL to track small perturbations in input and voltage-temperature conditions during normal operation while providing high immunity again circuit noise that principally dictate jitter performance.
In a PLL employing coarse and fine control of a varactor-tuned VCO, a calibration procedure is invoked prior to normal operation. During the calibration procedure, the PLL is “opened”, and capacitance is incrementally added or subtracted from the coarse control group to arrive at a net capacitance that causes the VCO to generate a frequency that is within the PLL's frequency capture range. By doing so, the PLL should be able to track input perturbations using only fine control.
During the calibration process, the fine control reference signal should ideally be set to a voltage level that will cause the associated group of fine control varactor capacitor cells to be centered with respect to the net capacitive tuning range of the group. By being centered within its capacitive tuning range, the fine control group of capacitor cells provides the varactor/VCO with maximum bi-directional tunability as well as gain linearity. However, due to PVT fluctuations, establishing this ideal, or “centered”, fine control reference voltage is not a trivial procedure. This is especially true for varactors exhibiting non-linear capacitance-versus-voltage characteristics, such as MOS inversion-mode varactors.
Several techniques are employed to achieve a “centered” fine control reference voltage during the calibration procedure. One such technique employs a calibration algorithm to empirically determine the fine control tuning range. There are variations in such algorithms, but one algorithm is described generally as follows:                a. Force the fine control reference voltage, VFINE, to one extreme, for instance, VFINE, MIN.        b. Determine the coarse control voltage difference, ΔVCOARSE,FINE, corresponding to the entire voltage tuning range of the fine control, ΔVFINE, MAX–ΔVFINE, MIN.        c. Calibrate the coarse control to determine the correct coarse control reference voltage, VCOARSE, that sets the VCO frequency to match the input reference frequency.        d. Add a value equal to ½×ΔVCOARSE,FINE back to ΔVCOARSE.        e. Close, or release, the PLL to lock to the input reference frequency. When the PLL achieves phase-lock, the fine control reference voltage will have drifted back from VFINE, MIN to an intermediate value, VFINE, LOCK, that should be equal to the “centered” fine control reference voltage.        
Though clever in overcoming PVT fluctuations, this technique adds significant complexity to the calibration procedure.
A second and much simpler technique involves using a resistive divider (e.g., two diode-connected transistors in series), which behave like resistors, and tapping the intermediate voltage. However, this technique is susceptible to PVT fluctuations since the PVT fluctuations in the voltage-dividing elements are not likely to track those of the varactor.